1. Technical Field
This application generally relates to electrical switching devices made using fabrics of carbon nanotube elements, which can serve as storage elements in nonvolatile memory devices.
2. Discussion of Related Art
Metal-oxide-semiconductor field-effect transistors (MOSFETs) are ubiquitous in modern electronics. These transistors possess the simultaneous qualities of bistability, high switching speed, low power dissipation, high reliability, and scalability to small dimensions. However, one feature not typical of MOSFETs is the ability to retain a digital state (e.g., a memory state) in the absence of applied power. As such, MOSFETs are frequently paired with other elements that are capable of storing a digital state. For example, flash memory cells resemble MOSFETS, but also include an insulated floating gate that is interposed between the control gate and the MOSFET channel and holds a charge representative of a digital state. Because this charge partially screens the control gate's electrical field, the digital state can be determined by measuring the voltage or current across the MOSFET channel. However, flash memory has a finite number of read/write cycles, leading to low long-term reliability; additionally, although each flash memory cell can be written and read independently, erase and rewrite operations must be performed on blocks of cells. Dynamic random access memory (DRAM) include MOSFETs coupled to capacitors that stores digital states as charge. Because the charge gradually leaks from the capacitors, the states must be refreshed periodically, e.g., every 64 ms or less, requiring separate circuitry. As such, in the absence of electrical power, DRAM loses the stored states; that is, the memory is volatile. Other conventional memory devices suffer from similar, or other, deficiencies.
There is also an ever-increasing demand to reduce the size of MOSFET arrays, enabling ever-greater numbers of devices (e.g., state-storing devices, such as memory cells) to be fabricated in a given area. This demand challenges the semiconductor industry to move to denser technology nodes, having smaller line and spacing dimensions and requiring improved alignment between layers. MOSFETs and associated storage elements must be scaled to smaller dimensions and/or redesigned. Additionally, because smaller devices have an increased sensitivity to defects, the density of defects generated during the manufacturing process needs to be reduced correspondingly.
U.S. Patent Application Publication No. 2008/0012047 discloses two-terminal switching devices that include first and second conductive terminals and a nanotube article, wherein at least a portion of the nanotube article overlaps the conductive terminals. Suitable application of electrical stimuli can change the relative resistance of the nanotube article between a relatively high resistance state and a relatively low resistance state.
U.S. Pat. No. 7,479,654 discloses a memory array that includes a plurality of memory cells, each of which receives a bit line, a first word line and a second word line. Each memory cell also includes a two-terminal switching device that includes first and second conductive terminals in electrical communication with a nanotube article.
U.S. patent application Ser. No. 12/486,602, filed Jun. 17, 2009 and entitled “NRAM Arrays with Nanotube Blocks, Nanotube Traces, and Nanotube Planes and Methods of Making Same,” discloses nanotube memory arrays that include a nanotube fabric layer disposed in electrical communication with first and second conductor layers. A circuit induces a change in the resistance of the nanotube fabric layer between the first and second conductor layers. Two adjacent memory cells can be formed in at least two selected cross sections of the nanotube fabric and conductor layers such that each memory cell is uniquely addressable and programmable. A change in resistance corresponds to a change in an informational state of the memory cell.